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MyHDL

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http://docs.myhdl.org/en/stable/manual/conversion.html

Anchor text: Conversion to Verilog and VHDL — MyHDL 0.11 documentation

Wikipedia: MyHDL

http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-of-test-benches

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http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-of-lists-of-signals

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http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-output-verification

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http://docs.myhdl.org/en/stable/manual/cosimulation.html

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http://docs.myhdl.org/en/stable/manual/conversion_examples.html

Anchor text: Conversion examples — MyHDL 0.11 documentation

Wikipedia: MyHDL